1. Field of the Invention
The present invention relates to an inverter control circuit and more particularly to an inverter control circuit which controls the output of the inverter based on waveform patterns stored in a storage element.
2. Description of the Prior Art
As a control circuit of this type, there is one in use as shown in FIG. 1. Referring to the drawing, reference numeral 1 denotes a frequency command circuit, 2 denotes a rate multiplier, 3 denotes an oscillator, 4 denotes a frequency divider, 5 denotes a counter, 6 denotes a read only memory (hereinafter to be called a ROM), 7 denotes a sexenary ring counter, and 8 denotes a data selector.
Now, operation of the inverter control circuit in FIG. 1 will be described. An 8-bit output from the frequency command circuit 1 is sent to the rate multiplier 2. The output signal F.sub.0 from the rate multiplier 2 is given by the followihg equation (1): ##EQU1## where K is a constant depending on the 8-bit input signal to the rate multiplier 2 and F.sub.i is the output frequency from the oscillator 3. The frequency F.sub.0 of the output signal from the rate multiplier 2 is divided by the frequency divider 4 into a predetermined output frequency F.sub.CK and then input to the counter 5. Here, if the case where the ROM 6 is of 12 bits and therefore has a storage capacity of 4096 words, for example, is considered, the ROM 6 will then have data stored therein such that one period of an a.c. control signal divided by 6 at intervals of 60.degree. in electrical angle as shown in FIG. 2 will be output therefrom corresponding to the first to sixth bits out of the eight bits of the output of the ROM 6. The 6-bit signals output from the ROM 6 are input to the data selector 8, where data selection is made in response to an output signal from the sexenary ring counter 7, which operates taking the eighth bit frequency F.sub.8 of the counter 5 as its clock, so that an a.c. control signal for a duration of one period is formed. The a.c. control signal for the remaining two phases at a lagged angle of 120.degree. and at another lagged angle of 120.degree. is formed likewise, and thus, a digital 3-phase a.c. signal is output therefrom.
Here, the frequency F.sub.CK is decided to be such that the eighth bit frequency F.sub.8 of the counter 5 will take the frequency which will be expressed by the following equation corresponding to a 60.degree. electrical angle of the a.c. control signal: ##EQU2## Then, the data corresponding to the 60.degree. electrical angles of the a.c. control signals can be stored in 256 divisions and 0.24.degree. electrical angle resolution (60.degree./256.apprxeq.0.24.degree.) is obtained.
While the prior art inverter control circuit is structured as described above, the voltage resolution (8 bits=6 bits+2 bits (clock, etc.)) of the inverter for its output voltage is such that only 16 sorts of output voltages can be provided, since, when using the ROM (4,096 words) to which 12 bits are input, the voltage control is made only by the remaining 4 bits. Therefore, for variations in frequencies from 0 to 60 Hz, for example, the output voltage can only be varied at 4 Hz intervals. Accordingly, there has been a disadvantage in the prior art that the V/f characteristic which is an essential characteristic to an inverter has been such that the same is only capable of coarse controlling to vary the output voltages at 4 Hz frequency intervals.